Risc-v, The Third Largest CPU Architecture, Has Entered Supercomputing With Remarkable Performance

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A team of European college students assembled the first risc-v supercomputer that could balance power consumption and performance. More importantly, it shows the great potential of risc-v in high-performance computing and provides an opportunity for Europe to get rid of its dependence on American chip technology. The "Monte Cimone" cluster will not be used to deal with large-scale weather simulation soon, because it is just an experimental machine.

This device is built by personnel from the University of Bologna and cineca, Italy's largest Supercomputing Center. It is designed as a six node cluster to demonstrate various HPC performance elements except floating-point capabilities.

It uses the power module of the freedom u740 system on chip risc-v of sifive. The SOC launched in 2020 has five 64 bit risc-v CPU cores - four U7 application cores and one S7 system management core - 2MB L2 cache, Gigabit Ethernet, and various peripheral devices and hardware controllers.

It can operate at a frequency of about 1.4GHz. The following are the components and speeds of Monte Cimone:

Six dual board servers with overall dimensions of 4.44cm (1U) high, 42.5cm wide and 40cm deep. Each board follows the industry standard Mini itx overall dimension (170 mm for every 170 mm);

Each motherboard is equipped with a sifive freedom u740 SOC and 16GB 64 bit DDR memory, with an operating speed of 1866s mt/s, a PCIe Gen 3 X8 bus with an operating speed of 7.8 gb/s, a Gigabit Ethernet port and a USB 3.2 Gen 1 interface;

Each node has an m.2 m-key expansion slot, which is occupied by the 1TB nvme 2280 SSD used by the operating system. Each board is inserted with a microSD card for UEFI startup;

Two 250 W power supplies are integrated inside each node to support hardware and future PCIe accelerators and expansion boards.

Top view of each node showing two sifive freedom SOC boards

The freedom SOC motherboard is essentially the hifive unmatched motherboard of sifive. As most supercomputers use, two of the six compute nodes are equipped with Infiniband host channel adapters (HCAs). The goal is to deploy 56gb/s Infiniband to allow RDMA to achieve i/o performance.

This is ambitious for a young architecture, and it is not without some minor problems.

"Suppliers currently only support PCIe Gen 3 channels," the cluster team wrote. "The first experimental result shows that the kernel can recognize device drivers and mount kernel modules to manage mellanox ofed stack. Since the incompatibility between software stack and kernel drivers has not been determined, we cannot use all RDMA functions of HCA.

Nevertheless, we have successfully run IB Ping tests between two boards and between one board and an HPC server, which shows that it is feasible to fully support Infiniband.

”Facts have proved that HPC software stack is easier than people think. "On Monte Cimone, we migrated all the basic services required to run HPC workloads in the production environment, namely NFS, LDAP and slurm job scheduler. It is relatively simple to migrate all the necessary software packages to risc-v.

The cluster will eventually pave the way for further testing the risc-v platform itself and its ability to work well with other architectures. This is an important element because we are unlikely to see a 10 billion level risc-v system in at least the next few years.

Now, even Intel is focusing on the future of risc-v.

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